This document is best-effort as the I2C registers are not publicly documented, and is based on testing and compiling public information. Always verify and test carefully at your own risk. If you come across errors or find new information, please leave a comment below.

1. I²C interface

Important rules:

• Wait until INT has remained HIGH for at least 100 ms before I²C access after wake-up.
• If INT goes LOW, stop accessing the IC within 16 ms.
• Modify registers using Read → Modify → Write.
• Do not alter reserved bits or undocumented registers.
• Default values can vary with peripheral configuration and IC configuration.
• For multi-byte live values, read the low byte first, then the high byte. Reading the low byte latches/updates the associated high byte.

2. Documented register map

Documentation ambiguity: 0x38 is labeled as read-only but simultaneously certain latched flags are cleared by setting them to 1. Verify on hardware before relying on write-to-clear behavior.

Addresses not listed above are not documented and should be treated as reserved/undocumented.

3. Read/write registers — detailed bit fields

0x00 — SYS_CTL0

0x01 — SYS_CTL1

0x02 — SYS_CTL2

Default code 0xAA = 170 corresponds to 4.20 V/cell.

0x03 — SYS_CTL3

Default code 0x61 = 97 corresponds to 9.7 A.

Do not set this below the actual intended charge/discharge current.

0x04 — SYS_CTL4

0x06 — SYS_CTL6

Default = 200 mA.

0x08 — SYS_CTL8

Vrch:

Chg_OvTime:

• 0: automatically disable charging after full charge; charging timeout remains active.
• 1: do not disable charging enable after full charge; charging timeout is removed.

0x09 — SYS_CTL9

Standby_Mode for D-version IC:

• 0: about 10 µA
• 1: about 100 µA
• default is 100 µA.

0x0A — SYS_CTL10

Base threshold:

ShutVol = (Set_BATlow + 25) × 100 mV × Ncells

Correction:

Vadjust = Adjust_Data × 100 mV

• Adjust_En = 0: ShutVol = base − Vadjust × Ncells
• Adjust_En = 1: ShutVol = base + Vadjust × Ncells

Settings below 2.7 V/cell provide software low-battery protection only.

0x0B — SYS_CTL11

USB-A/VOUT1 discharge during USB-C charging is not necessarily blocked by bit 7.

0x0C — SYS_CTL12

Power codes explicitly listed:

Inconsistency: the reset shown for Vbus_Snk_Power is 101b, while the visible table explicitly defines power codes only through 100b. Do not assume a meaning for 101b without hardware verification.

0x0D — SELECT_PDO

Codes:

Before selection, inspect 0x35. Selection becomes invalid when the adapter is unplugged and must then be determined/configured again.

Documentation ambiguity: the text describes making a selection but the access column is rendered as R. Verify whether the actual device accepts writes to this field.

0x10 — TEMP_LOOP_CTL

Threshold:

Tthreshold = 80 °C + N × 5 °C

0x15 — CC3CC4_CTL

For CC3/CC4:

• 0: LOW, internal 5.1 kΩ pull-down
• 1: HIGH via approximately 330 µA pull-up

Use these outputs only to drive MOS circuitry.

0x16 — STANDBY_TIME

Default = 10 s.

0x17 — NTC_CTL

0x22 — TypeC_CTL8

Role codes:

10 is not defined.

0x23 — TypeC_CTL9

All fields are R/W.

For the programmable-current enable bits, once enabled:

• advertised/output power is based on the configured PDO current;
• overcurrent is approximately 1.1 × configured PDO current.

0x24–0x28 — fixed-voltage PDO current settings

All fields occupy bits 7:0 and are R/W.

Default currents implied by the reset values:

• 0x96 = 150 → 3.00 A
• 0xFA = 250 → 5.00 A

0x29–0x2A — PPS PDO current settings

Default 0x3C = 60 → 3.00 A.

0x2B — TypeC_CTL17

0x2C — TYPEC_CTL18

Adds 10 mA to selected fixed-voltage PDO current settings; intended to be used together with the corresponding current-setting register.

4. Read-only status registers

0x31 — STATE_CTL0

Detailed 2:0 states:

0x32 — STATE_CTL1

0x33 — STATE_CTL2

Chg_Vbus:

000 and 111 are not defined/unknown.

0x34 — TypeC_STATE

Bits 3 and 2: QC5V/PD5V indication does not guarantee that fast charging succeeded.

0x35 — RECEIVED_PDO

Each PDO bit: 1 = yes, 0 = no.

0x38 — STATE_CTL3

For both fault bits:

• 1 indicates the event has occurred.
• Condition is considered valid after being detected more than twice within about 600 ms.
• From the event to system sleep is approximately 1.5 s.
• Bit needs to be set to 1 to clear it, despite classifying the section as read-only. Treat write-to-clear as needs hardware verification.

0x39 — IC_VERSION

0x3A — IC_TEMP

5. ADC / telemetry registers

Multi-byte read rule

For every two-byte measurement:

1. read the low-byte register first;
2. then read the associated high-byte register;
3. combine as:

raw = low | (high << 8)

Reading the low byte updates/latches both bytes so that the pair belongs to the same sample.

Voltage

Port currents

The port-current conversion assumes approximately 10 mΩ MOS internal resistance.

Timestamp

Battery current

IBAT = raw mA

System current

ISYS = raw mA

Minor naming inconsistencies (ISYSIADC, IVsysIADC, VsysIADC) relating to the same VSYS/system-current measurement pair.

System power

Psys = raw × 10 mW

NTC excitation current

0x77, bit 7 NTC_IADC_DAT:

Bits 6:0 are reserved.

NTC / GPIO0 ADC voltage

VGPIO0 = raw mV

Documented range: 0–3.3 V.

6. Useful derived defaults

Actual read-back defaults can differ according to the peripheral/configuration state; regard the value read from the IC as authoritative.

7. Firmware implementation notes

Safe register update

old = read_register(address)
new = (old & ~mask) | (desired_bits & mask)
write_register(address, new)

Do not overwrite reserved bits with hard-coded values.

Recommended read transaction behavior

wait until INT has been HIGH >= 100 ms
send device address
wait ~50 µs after ACK
read one register byte
NACK final byte
STOP
delay ~1 ms before next byte/register read

Example 16-bit telemetry

low  = read(0x50)
high = read(0x51)
vbat_mV = low | (high << 8)

8. Ambiguities worth testing on hardware

1. 0x0D Pdo_select is documented as selectable/configurable but the access column is shown as R.
2. 0x0C Vbus_Snk_Power reset appears as 101b, while the visible power-code list only defines 000 through 100.
3. 0x10 Temp_Loop_En has a malformed/shifted reset presentation.
4. 0x38 belongs to the read-only status section, yet bits 5 and 4 are described as cleared by writing 1.
5. A few current-register signal names vary between adjacent lines (ISYSIADC, IVsysIADC, VsysIADC).

These fields should be verified experimentally before firmware depends on the ambiguous behavior.

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