IP2366 I2C Register Map

This compilation is a best-effort and work in progress:

• Use entirely at own risk. There may - and will - be errors and inaccuracies and much of the information is infered, derived, tested, and interpreted.
• Add your own findings or corrections by leaving a comment below.

Reading this map

• All register addresses are hexadecimal, byte-wide addresses unless shown as a low/high pair.
• k is the numeric register field; S is the physical/configured series-cell count. This avoids the manuals’ ambiguous reuse of N for both.
• R/W means documented read/write. R means documented read-only. W1C? marks a text/table inconsistency concerning write-one-to-clear.
• Reset values below describe fields, not a byte to write blindly. Reserved bits must be preserved. Read actual power-up values; defaults can vary.
• A/B identifies documents agreeing on a field; B only means absent from A; lead means an implementation comment without a complete verified field definition.
• Unless a row explicitly lists reserved bits, all unlisted bits are reserved or undocumented. An unlisted address is not necessarily nonexistent.

Communication requirements

Item	Documented value or behavior	Implementation consequence
7-bit slave address	0x75	Use this with Arduino Wire and normal 7-bit APIs.
On-wire address bytes	Write 0xEA, read 0xEB	These include the R/W bit; do not pass 0xEA as a 7-bit address.
Logic voltage	3.3 V	A 5 V MCU requires level conversion.
Maximum clock	250 kHz; suggested 100–200 kHz	Start at 100 kHz.
Data preparation	Manuals request ACK checking and about 50 µs after address; recommend single-byte reads and about 1 ms between bytes	Wire-buffer delays before endTransmission() do not necessarily introduce gaps on the physical bus. Verify timing if communication fails.
Last received byte	Host sends NACK, then STOP	Required to end a read correctly.
Wake timing	Wait about 100 ms after INT is high	V1.00/B describe INT-high wake; other descriptions emphasize charging/EN wake. Confirm variant behavior.
Sleep indication	Stop I²C access within 16 ms of INT going low	Do not continuously poll a sleeping chip.
Sleep prevention	Manuals describe high INT as preventing sleep	Legacy package text claiming ground prevents sleep conflicts with this.
Reset command	0x00[6]=1; V1.00 specifies a 2 s wait	Re-read configuration afterward; not proof BAT_NUM is resampled.
Writes	Read, mask, modify, write only documented fields	Do not probe unknown registers with arbitrary writes.
Paired measurement reads	Read low byte first, then high; low-byte read refreshes both	Separate sequenced reads; combine low + (high << 8).
Multiple chips	Standard devices share 0x75; custom addresses require vendor customization	Two chips need separate buses, a mux, or verified distinct addresses. Do not assume your dual-chip board exposes both on one addressable bus.

System and charging controls

Address	Register / field	Bits	Access	Meaning / encoding	Field reset	Evidence
0x00	SYS_CTL0 / En_LOADOTP	7	R/W	1 reloads defaults on boot/wake; 0 retains settings through that mechanism. Manual discourages clearing without suitable reinitialization logic.	1	A/B
0x00	En_RESETMCU	6	R/W	Write 1 to reset registers to defaults; self-clears. Wait 2 s per A.	0	A/B
0x00	En_INT_low	5	R/W	1 enables an approximately 2 ms low INT exception indication.	0	A/B
0x00	En_Vbus_SinkDPdM	4	R/W	Input DP/DM fast-charge negotiation enable.	1	A/B
0x00	En_Vbus_SinkPd	3	R/W	Input PD negotiation enable.	1	A/B
0x00	En_Vbus_SinkSCP	2	R/W	Input SCP negotiation enable.	1	A/B
0x00	Reserved	1	Preserve	No usable definition.	0	A/B
0x00	En_Charger	0	R/W	1 enables charging; 0 disables charging. B’s translated parenthesis is awkward; A clearly describes no charging when disabled.	1	A/B
0x01	SYS_CTL1	Unknown	Unknown	D labels it series-cell count, battery type, current-setting mode. No bit allocation or coding established.	Unknown	D lead only
0x02	SYS_CTL2 / Vset	7:0	R/W	Per-cell target 2500 + 10k mV; maximum 4400 mV, so documented useful codes 0–190. Pack target nominally S × Vcell.	Unspecified	A/B
0x03	SYS_CTL3 / Iset	7:0	R/W	BAT-side charging-current limit 100k mA; documented maximum 9700 mA. Must not be below termination current.	0x61 = 9700 mA	A/B
0x04	SYS_CTL4	Unknown	Unknown	Defined in C as battery capacity; absent from both inspected IP2366 map PDFs and no verified accessor/encoding established.	Unknown	C lead only
0x06	SYS_CTL6 / Itk	7:0	R/W	Precharge/trickle current 50k mA. No independent trickle threshold or timeout field exposed here in the inspected PDFs.	0x04 = 200 mA	A/B
0x08	SYS_CTL8 / Istop	7:4	R/W	Termination current 50k mA; field 0–15 gives 0–750 mA. Zero is not documented as “disable termination.”	2 = 100 mA	A/B
0x08	Vrch	3:2	R/W	0 no recharge; 1 target − S×50 mV; 2 target − S×100 mV; 3 target − S×200 mV.	2	A/B
0x08	Reserved	1:0	Preserve	No usable definition.	Unspecified	A/B
0x09	SYS_CTL9 / En_Standby	7	R/W	1 permits standby; 0 disables it.	1	A/B
0x09	Standby	6	R/W	One-shot write 1 enters standby when not charging; requires bit 7 enabled.	0	A/B
0x09	En_BAT_Low	5	R/W	Enable fixed 5 V pack low-voltage shutdown; software protection only; also changes precharge-to-CC behavior.	0	A/B
0x0A	SYS_CTL10 / Set_BATlow	7:5	R/W	A: 0–4 = 2.8/2.9/3.0/3.1/3.2 V per cell; 5–7 unspecified. B: 0–7 = 2.5 through 3.2 V per cell in 0.1 V increments. Also affects precharge-to-CC threshold. B says ≤2.7 V has software-only low-voltage protection.	2, meaning differs	Conflicting A/B
0x0B	SYS_CTL11 / En_Dc-Dc_Output	7	R/W	1 enables discharge output; 0 disables it.	1	A/B
0x0B	En_Vbus_Src_DP_dM	6	R/W	Output DP/DM fast-charge enable.	1	A/B
0x0B	En_Vbus_SrcPd	5	R/W	Output PD enable.	1	A/B
0x0B	En_Vbus_SrcSCP	4	R/W	Output SCP enable.	1	A/B
0x0C	SYS_CTL12 / Vbus_Src_Power	7:5	R/W	Codes 0/1/2/3/4/5 = 30/45/60/65/100/140 W. Codes 6/7 undefined. A calls it input/output selection; B calls it output. A says writes interact with PDO settings: later writes override earlier ones.	5 = 140 W	A/B, scope wording differs
0x0D	SELECT_PDO / Pdo_select	2:0	Uncertain	B describes selecting input fixed PDO: 0/1/2/3/4 = 5/9/12/15/20 V. Check availability in 0x35 first. Highest adapter profile is default; re-identify/reconfigure after the configuration becomes invalid. B labels field R despite selection text; C implements writes.	Unspecified	B only + C; access contradiction

Theoretical BAT CV windows, assuming the selected cell count is actually active and charger operation allows the requested voltage:

Series count	Minimum target	Maximum target	Pack step
2S	5.00 V	8.80 V	20 mV
3S	7.50 V	13.20 V	30 mV
4S	10.00 V	17.60 V	40 mV
5S	12.50 V	22.00 V	50 mV
6S	15.00 V	26.40 V	60 mV

These are register arithmetic, not verified continuous bench-supply operating ranges. They do not demonstrate startup into zero volts, absence of termination, accuracy, or stability.

USB-C role and source PDO controls

Address	Register / field	Bits	Access	Meaning / encoding	Field reset	Evidence
0x22	TypeC_CTL8 / Vbus_Mode_Set	7:6	R/W	0 UFP/sink; 1 DFP/source; 3 DRP; 2 undefined.	A: 3; B: 0	A/B default conflict
0x23	TypeC_CTL9 / En_5VPdo_3A/2.4A	7	R/W	Default 5 V PDO current choice: 1 = 3 A; 0 = 2.4 A. Interaction with custom-current enable needs validation.	1	A/B
0x23	En_Pps2Pdo_Iset	6	R/W	Enable custom PPS2 current from 0x2A.	0	A/B
0x23	En_Pps1Pdo_Iset	5	R/W	Enable custom PPS1 current from 0x29.	0	A/B
0x23	En_20VPdo_Iset	4	R/W	Enable custom 20 V current from 0x28.	0	A/B
0x23	En_15VPdo_Iset	3	R/W	Enable custom 15 V current from 0x27.	0	A/B
0x23	En_12VPdo_Iset	2	R/W	Enable custom 12 V current from 0x26.	0	A/B
0x23	En_9VPdo_Iset	1	R/W	Enable custom 9 V current from 0x25.	0	A/B
0x23	En_5VPdo_Iset	0	R/W	Enable custom 5 V current from 0x24.	0	A/B
0x24	TypeC_CTL10 / 5VPdo_Iset	7:0	R/W	Source 5 V advertised current 20k mA, plus add bit from 0x2C[0]. B states maximum 3 A.	0x96 = 3 A	A/B
0x25	TypeC_CTL11 / 9VPdo_Iset	7:0	R/W	Source 9 V current 20k mA, plus 0x2C[1]. B maximum 3 A.	0x96	A/B
0x26	TypeC_CTL12 / 12VPdo_Iset	7:0	R/W	Source 12 V current 20k mA, plus 0x2C[2]. B maximum 3 A.	0x96	A/B
0x27	TypeC_CTL13 / 15VPdo_Iset	7:0	R/W	Source 15 V current 20k mA, plus 0x2C[3]. B maximum 3 A.	0x96	A/B
0x28	TypeC_CTL14 / 20VPdo_Iset	7:0	R/W	Source 20 V current 20k mA, plus 0x2C[4]. B maximum 5 A with cable recognition, otherwise 3 A.	0xFA = 5 A	A/B
0x29	TypeC_CTL23 / Pps1Pdo_Iset	7:0	R/W	PPS1 source advertised current 50k mA. B discusses up to 5 A with cable recognition, otherwise 3 A, but its default prose contradicts field value.	0x3C = 3 A, not 5 A	A/B
0x2A	TypeC_CTL24 / Pps2Pdo_Iset	7:0	R/W	PPS2 source current 50k mA; same caveat as PPS1.	0x3C = 3 A	A/B
0x2B	TypeC_CTL17 / En_Src_Pps2Pdo	6	R/W	Advertise PPS2 when 1.	1	A/B
0x2B	En_Src_Pps1Pdo	5	R/W	Advertise PPS1 when 1.	1	A/B
0x2B	En_Src_20VPdo	4	R/W	Advertise fixed 20 V when 1.	1	A/B
0x2B	En_Src_15VPdo	3	R/W	Advertise fixed 15 V when 1.	1	A/B
0x2B	En_Src_12VPdo	2	R/W	Advertise fixed 12 V when 1.	1	A/B
0x2B	En_Src_9VPdo	1	R/W	Advertise fixed 9 V when 1. Bits 7 and 0 are reserved.	1	A/B
0x2C	TypeC_CTL18 / EN_20VPDO_ADD	4	R/W	Add 10 mA to programmed 20 V PDO current.	0	A/B
0x2C	EN_15VPDO_ADD	3	R/W	Add 10 mA to 15 V PDO current.	0	A/B
0x2C	EN_12VPDO_ADD	2	R/W	Add 10 mA to 12 V PDO current.	0	A/B
0x2C	EN_9VPDO_ADD	1	R/W	Add 10 mA to 9 V PDO current.	0	A/B
0x2C	EN_5VPDO_ADD	0	R/W	Add 10 mA to 5 V PDO current.	0	A/B

For custom current settings, the manual describes output overcurrent protection at about 1.1 times the configured PDO current for the listed higher-voltage/PPS fields. This is not equivalent to a tightly regulated lab CC setpoint. Changing source advertisements may also require renegotiation; no universal live-update sequence was established.

Neither inspected map exposes a 28 V source-PDO current/enable field, AVS voltage request, or PPS minimum/maximum-voltage field. The broader chip family supports EPR according to F, but that does not fill these register-map gaps.

Status and partner capabilities

Address	Register / field	Bits	Access	Meaning	Evidence
0x31	STATE_CTL0 / CHG_En	5	R	Charging-context flag; VbusOk counts. Does not prove nonzero BAT current.	A/B
0x31	CHG_End	4	R	1 indicates full/charge complete.	A/B
0x31	Output_En	3	R	1 discharge output open without reported abnormality.	A/B
0x31	Chg_state	2:0	R	0 standby; 1 trickle; 2 CC; 3 CV; 4 waiting; 5 full; 6 timeout; 7 undefined.	A/B
0x32	STATE_CTL1 / Chg_State	7:6	R	0 = 5 V input charging; 1 = high-voltage fast charging. Other codes unspecified.	A/B
0x33	STATE_CTL2 / Vbus_Ok	7	R	VBUS powered/present.	A/B
0x33	Vbus_Ov	6	R	VBUS input overvoltage flag.	A/B
0x33	Chg_Vbus	2:0	R	Input-voltage category; conflicting codebooks below.	A/B conflict
0x34	TypeC_STATE / Sink_Ok	7	R	Valid Type-C sink connection.	A/B
0x34	Src_Ok	6	R	Valid Type-C source connection.	A/B
0x34	Src_Pd_Ok	5	R	Source-side PD connection valid.	A/B
0x34	Sink_Pd_Ok	4	R	Sink-side PD connection valid.	A/B
0x34	Vbus_Sink_Qc_Ok	3	R	Input fast-charge flag; QC5V/PD5V excluded from fast-charge indication.	A/B
0x34	Vbus_Src_Qc_Ok	2	R	Output fast-charge flag; QC5V/PD5V excluded.	A/B
0x35	RECEIVED_PDO / PDO_20V	4	R	Received/available fixed 20 V PDO flag. No current value.	B only + C
0x35	PDO_15V	3	R	Fixed 15 V received/available.	B only + C
0x35	PDO_12V	2	R	Fixed 12 V received/available.	B only + C
0x35	PDO_9V	1	R	Fixed 9 V received/available.	B only + C
0x35	PDO_5V	0	R	Fixed 5 V received/available. Bits 7:5 reserved.	B only + C
0x38	STATE_CTL3 / Vsys_Oc	5	R / W1C?	Latched output overcurrent; prose says write 1 to clear despite R column.	A/B inconsistency
0x38	Vsys_Scdt	4	R / W1C?	Latched output short-circuit; same access inconsistency.	A/B

0x38 describes repeated fault detections within roughly 600 ms and approximately 1.5 s before sleep. B’s fault-recovery prose refers to toggling 0x22[7], but its own map defines 0x22[7:6] as the Type-C role. Treat that recovery instruction as suspect; do not implement it blindly.

Conflicting 0x33[2:0] codebooks

Code	A: V1.00	B: V1.13 English / C decoder
0	Unspecified	Unspecified
1	5 V	Unspecified
2	7 V	5 V
3	9 V	7 V
4	12 V	9 V
5	15 V	12 V
6	20 V	15 V
7	28 V	20 V

Use measured 0x52/0x53 voltage and known adapter profiles to identify the codebook your chip uses. A higher document version number does not prove it matches your chip or that every entry is correct.

Measurements and identification bytes

Address(es)	Register(s)	Access	Format / units	Evidence / caveat
0x50, 0x51	BATVADC_DAT0/1	R	Low then high; combined value in mV at VBAT.	A/B
0x52, 0x53	VsysVADC_DAT0/1	R	Low then high; combined value in mV at VSYS.	A/B; confirm actual board node and voltage drop to USB VBUS.
0x69	TIMENODE1	R	First ASCII identification/time-node character.	B only + C
0x6A	TIMENODE2	R	Second ASCII character.	B only + C
0x6B	TIMENODE3	R	Third ASCII character.	B only + C
0x6C	TIMENODE4	R	Fourth ASCII character.	B only + C
0x6D	TIMENODE5	R	Fifth ASCII character.	B only + C; not established as a live clock or formal version ID.
0x6E, 0x6F	IBATIADC_DAT0/1	R	Low then high; combined BAT current in mA.	A/B; signedness/direction coding not specified.
0x70, 0x71	ISYS_IADC_DAT0 / IVsys_IADC_DAT1	R	Low then high; combined system-side current in mA.	A/B; inconsistent naming; signedness not specified.
0x74, 0x75	Vsys_POW_DAT0/1	R?	A gives combined power in 10 mW units.	B mistranslates battery level as power in the revision history. Chinese V1.14 confirms the removed feature is battery-level reading, not power telemetry. A gives 10 mW units; validate on the actual chip.
0x77	INTC_IADC_DAT0 / NTC_IADC_DAT	R	Bit 7: 0 = 20 µA excitation; 1 = 80 µA. Bits 6:0 reserved.	A/B; this is an excitation-current indication, not battery current.
0x78, 0x79	VGPIO0_NTC_DAT0/1	R	Low then high; GPIO0/NTC voltage in mV, nominal 0–3300 mV.	A/B; no additional 3300/65535 scaling is specified.

Read pairs in separate explicit statements so language expression-evaluation order cannot reverse them. Decode direction from validated status until a signed current encoding is established. NTC voltage plus excitation current can yield resistance; converting that to temperature requires the actual thermistor curve and board network.

Undocumented or questionable address leads

These rows are intentionally separated from the documented map. They are not permission to write these locations, and names alone do not determine whether they are configuration commands, raw GPIO ADC readings, or copied definitions for another chip.

Address	Claimed name / purpose	What remains unknown	Source
0x01	SYS_CTL1: series count, battery type, current-setting mode	Bits, encoding, access, prerequisites, reset behavior, firmware applicability. Unused definition; matches an IP2368 heading. No verified cell-count field.	D
0x04	SYS_CTL4: battery capacity	No usable encoding verified. Could be inherited/stale definition.	C
0x54	IVBUS_IADC: input charging current	Width, scale, access, relevance; absent from A/B.	D
0x7A	VGPIO1_ISET: current setting	May be configuration-pin ADC data rather than writable current command. GPIO1 is INT in standard IP2366 I²C pinout, raising concern.	D
0x7C	VGPIO2_VSET: cell-voltage setting	Access and scale unknown; may be GPIO voltage telemetry.	D
0x7E	VGPIO3_FCAP: battery capacity	Conflicts with usual IP2366 GPIO3/PSET function.	D
0x80	VGPIO4_BATNUM: cell-count setting	No bit definition; name is consistent with BAT_NUM pin but does not prove writable S. Do not infer codes 2–6.	D

D also calls 0x35 MOS_STATE, conflicting with B/C’s RECEIVED_PDO. Together with the GPIO labels, this reduces confidence in its unexercised header definitions. A candidate address is evidence worth investigating, not a verified extension of the manufacturer map.

Revision history and incompatibilities

B lists: V1.00 2023-03-24; V1.10 2023-04-18 adds charge-PDO selection; V1.11 2023-04-24 removes battery-level reading as unsupported (the English translation incorrectly calls this power); V1.12 2023-06-13 changes standby/wake-related instructions; V1.13 2023-06-26 extends low-voltage selection down to 2.5 V. These dates are the document’s own history, not independently verified firmware-release dates.

Topic	Difference	Practical consequence
Input fixed PDO	B adds 0x0D and 0x35.	Earlier statement that only automatic input selection is possible was incomplete.
Low-voltage selection	A starts at 2.8 V/cell; B at 2.5 V/cell.	Same bits can imply a 0.3 V/cell difference.
Voltage status	A includes 28 V; B shifted codes omit it.	A decoder copied from C can misreport an A-style chip.
Role reset	A DRP; B UFP.	Read your actual initial state.
Power telemetry	B mistranslates the deleted battery-level feature as power. Chinese V1.14 resolves the wording.	Power telemetry is not shown to be unsupported by that revision entry.
PPS current default	0x3C × 50 mA = 3 A, B prose says 5 A.	Trust arithmetic, then actual advertisements; do not repeat prose as a measured default.
SELECT_PDO access	B calls it selection but marks field R.	C’s implementation supports the intended interpretation, but hardware confirmation is still required.
Fault clear	Both text and access column disagree.	Verify W1C behavior before designing recovery.

F lists B, C, and D silicon/firmware families. ENP and STB variants differ in wake behavior and standby consumption; C variants require charging activation, and F recommends migration to D. It explicitly requires matching chip and firmware versions. Package markings such as your “993 00DY” and “323 00DY” were not reliably decoded by the sources inspected, so neither marking proves this map’s applicability.

The repository also contains IP2368 V1.61/V1.63 documents. They are not IP2366 register revisions. Similar names do not justify importing IP2368-only controls into this map.

Focused follow-up: register 0x01 (2026-10-05)

The initial 0x01 lead does not survive source inspection as evidence of a working IP2366 cell-count command. The Byoreh_94 STM32 header defines the address, but the posted implementation has no read/write call using that definition. Its initialization only configures GPIOs; its data-reading state machine polls status and ADC values. A generic WriteOneByte helper is present, but no concrete 0x01 invocation is shown.

The wording “series number setting, battery type, current setting mode” matches the IP2368 SYS_CTL1 heading. That IP2368 document nevertheless lists upper bits as reserved and only four chemistry/mode fields. Copying that heading is a plausible explanation for the IP2366 header comment; its provenance is not proved.

Most complete bit definition found: IP2368 only

This is a comparison, not an IP2366 map.

Bits	Name	Mask	IP2368 meaning	Reset
7:4	Reserved	0xF0	Preserve; no exposed cell-count encoding	Unspecified
3	En_BATmode_set	0x08	Enable register-defined battery chemistry	0
2	Set_BATmode	0x04	0 LiFePO4, 1 ordinary Li-ion; changes chemistry-dependent voltage behavior	1
1	En_Isetmode_set	0x02	Enable selection of current-versus-power interpretation	0
0	Set_Isetmode	0x01	0 BAT charging current, 1 input charging power; affects 0x03[6:0]	1

GitHub projects and implementation resources

Resource	What is present	Assessment
D-314/IP2368-Arduino-Library	MIT Arduino library, IP2366/IP2368 classes, raw register access, read examples, error-handling examples, extended-read examples, PDFs and editable translated documents.	The strongest inspected public firmware resource. README says write functions are not fully tested.
Legacy D-314/IP2366-Arduino-Library	Referenced by the deprecated PlatformIO package.	Historical lead; use the combined repository as the inspected implementation. Do not count this as an independent corroboration.
Release history	IP2366 support added in 1.2.0; later releases mention power-reading and other fixes.	Useful history, not proof all remaining accessors are correct.
Issue #3: inactive I²C on some boards	Variant-dependent I²C discussion.	Chip identity/firmware matters; replacing LED wiring cannot establish that every chip supports I²C.
Issue #4: IP2366 support	IP2366 integration and board discussion.	Relevant connection reference; map the actual PCB rather than copying resistor numbers blindly.
IP2366 examples	SimpleDataRead, ErrorHandling, ExtendendDataRead.	Starting points for read-only exploration.
PlatformIO legacy package	Deprecated IP2366 package description.	Contains an INT-to-ground sleep claim conflicting with manufacturer text. Follow measured board behavior and the primary manual.

Source index

Links below are ordinary public URLs. “Inspected” means the document or code was actually retrieved and read; “lead” means availability or attached content was not verified.

ID	Source	Status and value
A	Injoinic IP2366 register document V1.00, 18 pages	Inspected PDF. Revision dated 2023-03-24. Primary manufacturer text hosted by a third party. Baseline map.
B	IP2366 I2C regs V1.13 EN.pdf	Inspected from a local clone; 12 pages. English document distributed by the library author; manufacturer headings, but translation provenance and correspondence to any specific chip firmware are unverified. Revision history ends 2023-06-26.
B2	Editable V1.13 English DOCX	Exists in inspected repository; PDF was used for this map.
C	D-314 IP236x Arduino repository	Inspected code, examples, and bundled PDFs. Repository name remains IP2368, but supports both chips.
C1	IP2366.cpp	IP2366-specific accessors and register constants.
C2	IP236x.cpp	Shared accessors, status decoding, ADC reads.
D	Byoreh_94: STM32 IP2366 driver and data reading	Inspected author-posted C/header code, dated 2025-07-04. Supplies 0x01 and additional register-name leads; contains conflicts with PDFs.
E	ql君/qlexcel: IP2366 explanation and practical experiments	Inspected author’s account, including BAT-side electronic-load startup experiment and communication notes.
F	ChipSourceTek variant/version selection document	Inspected 4-page distributor document, dated 2024-01-25. Distinguishes B/C/D and ENP/STB variants.
G	LCSC IP2366 I²C datasheet	General datasheet lead; includes pin and resistor configuration. Not an additional verified register map.
H	IP2366_DEMO_V1.41 schematic	Indexed manufacturer schematic lead, useful for BAT_NUM and I²C pin routing. V1.41 is a schematic revision, not a register-map revision.
I	Verified IP2366 EVM by yizhidianzi	Indexed project description advertises exposed test points and an attached I²C manual; direct retrieval returned 403, attachments not inspected.
J	原同学: bidirectional converter main power board	Inspected author project page, dated 2023-09-22. IP2366 I²C, GD32E230 firmware, display daughterboard, and listed firmware archive; archive not downloaded.
K	ZHAO-POWER-H1 project	Indexed author project description: two IP2366 I²C devices, STM32 controller, additional ports. Software section explicitly says implementation was unfinished.
L	ChipSourceTek original register-PDF endpoint	Direct web retrieval returned 403. Do not assume identical contents to A or B.

The inspected GitHub snapshot is commit 9a23b86ec0f2544c56b25e16900b5257347a150a. For reproducibility, replace main in GitHub links with this commit. No exhaustive claim is made about private customer manuals, QQ group files, unindexed repositories, or chip-specific customized firmware.

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