The First ESP Microcontroller Based on RISC-V Architecture And A Very Fast One-Core CPU

In 2020, Expressif released both the S-Series and the first member of the C-Series.

C3 - RISC-V Architecture

The ESP32 C3 marks a fundamental change in processor architecture as it now uses RISC-V. The C3 is a very fast one-core microcontroller.

ESP32 C3 produced by Seeed

Changes Compared To ESP32 WROOM/WROVER

Here is the list of removed or reduced features compared to ESP32:

Feature Removal
Cores 1 instead of 2
Frequency reduced from 240 to 160
SRAM reduced from 520 to 400
ROM reduced from 448 to 384
RTC RAM reduced from 16 to 8
GPIOs reduced from 34 to 22
LED PWM reduced from 16 to 6
UART reduced from 3 to 2
SPI reduced from 4 to 3
ADC reduced channels from 18 to 6
Motor PWM removed
Touch removed
DAC removed
SD support removed
Hall Sensor removed
Ethernet removed
Camera support removed

New Features

This is what’s new:

Feature Addition
Bluetooth BLE v5.0 instead of BLE v4.2
WiFi WiFi-Alliance/WPA 3 certified
Temperature Sensor added
SD Host extended from 1 to 2
USB OTG added


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(content created Mar 23, 2024)